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1 typical a pplica t ion descrip t ion dual 4 mhz, 3 a synchronous step-down dc/dc converter the lt c ? 3615/ltc3615-1 are dual 3 a synchronous step- down regulators using a current mode, constant - frequency architecture. the dc supply current is only 130a (burst mode operation at no-load) while maintaining the output voltages, dropping to zero current in shutdown. the 2.25v to 5.5 v input supply range makes the parts ideally suited for single li-ion applications . 100% duty cycle capability provides low dropout operation, which extends operating time in battery-operated systems. the operating frequency is externally programmable up to 4mhz, allowing the use of small surface mount inductors. 0 , 90 , or 180 ( ltc3615) or 140/180 ( ltc3615-1) of phase shift between the two channels can be selected to minimize input current ripple and output voltage ripple in a dual 3 a or single 6 a output configuration. programmable slew rate limiting reduces emi, and external synchroniza - tion can be applied up to 4mhz. the internal synchronous switches increase efficiency and eliminate the need for external catch diodes, saving external components and board space. the ltc3615/ltc3615-1 are offered in leadless 24-pin 4mm 4 mm qfn and thermally enhanced 24- pin tssop packages. efficiency and power loss vs load current fea t ures a pplica t ions n high efficiency: up to 94% n dual outputs with 2 3a output current capability n low output ripple burst mode ? operation : i q = 130a n 2.25v to 5.5v input voltage range n 1% output voltage accuracy n output voltages down to 0.6v n programmable slew rate at switch pins n low dropout operation: 100% duty cycle n shutdown current 1a n adjustable switching frequency up to 4mhz n internal or external compensation n selectable pulse-skipping/forced continuous/ burst mode operation with adjustable burst clamp n optional active voltage positioning ( avp ) with internal compensation n selectable 0/90/180 ( ltc3615) or selectable 140/180 ( ltc3615-1) phase shift between channels n fixed internal and programmable external soft-start n accurate start-up tracking capability n ddr memory mode i out = 1.5a n available in 4 mm 4 mm qfn-24 and tssop-24 packages n point-of-load supplies n distributed power supplies n portable computer systems n ddr memory termination n handheld devices sw1 fb1 ltc3615 3615 ta01a sgnd pgnd run1 track/ss1 ith1 phase run2 track/ss2 pgood2 ith2 pgood1 srlim r t /sync mode v in sv in pv in1 pv in2 100f sw2 fb2 0.47h 47f v out2 2.5v/3a 665k 210k 0.47h 47f v out1 1.8v/3a 422k 210k l, lt , lt c , lt m , linear technology, burst mode and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5994885, 6304066, 6498466, 6580258, 6611131. output current (a) 30 efficiency (%) power loss (w) 90 100 20 10 80 50 70 60 40 0.001 0.1 1 3615 ta01b 0 10 0.001 0.0001 1 0.1 0.01 0.01 v in = 3.3v v in = 4v v in = 5v 2.25mhz v out = 2.5v ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
2 a bsolu t e maxi m u m r a t ings pv in 1 , pv in 2 voltages .................... C 0. 3 v to sv in + 0.3 v sv in voltage ................................................ C 0. 3 v to 6v sw1 voltage ............................. C 0. 3 v to ( pv in 1 + 0.3 v) sw2 voltage .............................. C 0. 3 v to ( pv in 2 + 0.3 v) pgood 1, pgood 2 voltages ........................ C 0. 3 v to 6v all other pins .............................. C 0. 3 v to ( sv in + 0.3 v) (notes 1, 11) 1 2 3 4 5 6 7 8 9 10 11 12 top view fe package 24-lead plastic etssop 24 23 22 21 20 19 18 17 16 15 14 13 phase fb2 ith2 track/ss2 sgnd pv in2 pv in2 sw2 sw2 run2 run1 r t /sync mode fb1 ith1 track/ss1 sv in pv in1 pv in1 sw1 sw1 pgood1 srlim pgood2 25 pgnd t jmax = 150c, ja = 33c/w exposed pad ( pin 25) is pgnd, must be soldered to pcb 24 23 22 21 20 19 7 8 9 top view uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 ith1 fb1 mode phase fb2 ith2 pgood1 srlim pgood2 r t /sync run1 run2 track/ss1 sv in pv in1 pv in1 sw1 sw1 track/ss2 sgnd pv in2 pv in2 sw2 sw2 25 pgnd t jmax = 150c, ja = 37c/w exposed pad (pin 25) is pgnd, must be soldered to pcb p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3615efe#pbf ltc3615efe#trpbf ltc3615fe 24-lead plastic tssop C40c to 125c ltc3615ife#pbf ltc3615ife#trpbf ltc3615fe 24-lead plastic tssop C40c to 125c ltc3615hfe#pbf ltc3615hfe#trpbf ltc3615fe 24-lead plastic tssop C40c to 150c ltc3615mpfe#pbf ltc3615mpfe#trpbf ltc3615fe 24-lead plastic tssop C55c to 150c ltc3615euf#pbf ltc3615euf#trpbf 3615 24-lead (4mm 4mm) plastic qfn C40c to 125c ltc3615iuf#pbf ltc3615iuf#trpbf 3615 24-lead (4mm 4mm) plastic qfn C40c to 125c ltc3615huf#pbf ltc3615huf#trpbf 3615 24-lead (4mm 4mm) plastic qfn C40c to 150c ltc3615mpuf#pbf ltc3615mpuf#trpbf 3615 24-lead (4mm 4mm) plastic qfn C55c to 150c ltc3615efe-1#pbf ltc3615efe-1#trpbf ltc3615fe-1 24-lead plastic tssop C40c to 125c ltc3615ife-1#pbf ltc3615ife-1#trpbf ltc3615fe-1 24-lead plastic tssop C40c to 125c ltc3615hfe-1#pbf ltc3615hfe-1#trpbf ltc3615fe-1 24-lead plastic tssop C40c to 150c ltc3615mpfe-1#pbf ltc3615mpfe-1#trpbf ltc3615fe-1 24-lead plastic tssop C55c to 150c ltc3615euf-1#pbf ltc3615euf-1#trpbf 36151 24-lead (4mm 4mm) plastic qfn C40c to 125c LTC3615IUF-1#pbf LTC3615IUF-1#trpbf 36151 24-lead (4mm 4mm) plastic qfn C40c to 125c ltc3615 huf-1#pbf ltc 3615huf-1#trpbf 36151 24-lead (4mm 4mm) plastic qfn C40c to 150c ltc3615mpuf-1#pbf ltc3615mpuf-1#trpbf 36151 24-lead (4mm 4mm) plastic qfn C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating junction temperature range ( notes 2, 11) ............................... C 5 5 c to 150 c storage temperature .............................. C 65 c to 150 c lead soldering temperature ( etssop ) ................. 30 0 c reflow peak body temperature ( qfn ) .................. 26 0 c ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
3 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v in operating voltage range l 2.25 5.5 v v uvlo undervoltage lockout threshold sv in ramping down l 1.7 v sv in ramping up 2.25 v v fb feedback voltage internal reference (note 3) v track = sv in , v srlim = 0v 0c < t j < 85c C40c < t j < 125c C55c < t j < 150c l l 0.592 0.590 0.588 0.6 0.608 0.610 0.612 v v v feedback v oltage external reference (note 7) (note 3) v track = 0.3v, v srlim = sv in 0.289 0.3 0.311 v (note 3) v track = 0.5v, v srlim = sv in 0.489 0.5 0.511 v i fb feedback input current v fbx = 0.6v l 0 30 na ?v linereg line regulation sv in = pv inx = 2.25v to 5.5v (note 4) l 0.2 %/ v ?v loadreg load regulation v ithx from 0.5v to 0.9v (note 4) v ithx = sv in , v fbx = 0.6v (note 5) 0.2 2 % % i s active mode v fb1 = 0.5v, v mode = sv in , v run2 = 0v (note 6) 1100 a v fbx = 0.5v , v mode = sv in , v runx = sv in ( note 6) 1900 a sleep mode v fb1 = 0.7v, v run1 = sv in , v run2 = 0v, v mode = 0v, v ith1 = sv in (note 5) 95 130 a v fbx = 0.7v, v run1 = sv in , v run2 = 0v, v mode = 0v (note 4) 145 220 a v fbx = 0.7v, v runx = sv in , v mode =0v, v ithx = sv in (note 5) 130 200 a v fbx = 0.7v, v runx = sv in , v mode =0v, i th = (note 4) 240 360 a shutdown sv in = pv in = 5.5v, v runx = 0v 0.1 1 a r ds(on) top switch on-resistance pv inx = 3.3v (note 10) 75 m bottom switch on-resistance pv inx = 3.3v (note 10) 55 m i lim top switch current limit sourcing (note 8), v fb = 0.5v duty cycle <35% duty cycle = 100% 4.5 3.6 6 7.5 a a bottom switch current limit sinking (note 8), v fb = 0.7v, forced continuous mode C2.5 C3.5 C5 a i sw(lkg) switch leakage current sv in = pv in = 5.5v, v runx = 0v 0.01 1 a g m(ea) error amplifier transconductance C5a < i th < 5a 240 mho i ea error amplifier output current (note 4) 30 a t soft-start internal soft-start time v fbx from 0.06v to 0.54v, track/ssx = sv in 0.65 1.1 1.7 ms r dis track/ss pull-down resistance at start-up 200 t dis soft- start discharge time at start- up 70 s f osc internal oscillator frequency r rt /sync = 178k l 1.85 2.25 2.65 mhz v rt /sync = sv in l 1.8 2.25 2.7 mhz f sync synchronization frequency t low , t high > 30ns 0.4 4 mhz v rt /sync sync level high 1.2 v sync level low 0.3 v the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2), sv in = pv inx = 3.3v, r t = 178k, r srlim = 40.2k, unless otherwise specified. ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
4 symbol parameter conditions min typ max units j sw1Csw2 output phase shift between sw1 and sw2 (ltc3615) v phase < 0.15 ? sv in 0 deg 0.35 ? sv in < v phase < 0.65 ? sv in 90 deg v phase > 0.85 ? sv in 180 deg output phase shift between sw1 and sw2 (ltc3615-1) v phase < 0.65 ? sv in 140 deg v phase > 0.85 ? sv in 180 deg v srlim voltage at srlim to enable ddr mode (note 9) sv in C 0.3 v v mode (note 9) internal burst mode operation 0.3 v pulse-skipping mode sv in C 0.3 v forced continuous mode 1.1 sv in ? 0.58 v external burst mode operation 0.5 0.85 v pgood power good voltage windows track/ssx = sv in , entering window v fbx ramping up v fbx ramping down C3.5 3.5 C6 6 % % track/ssx = sv in , leaving window v fbx ramping up v fbx ramping down 9 C9 11 C11 % % t pgood power good blanking time entering/leaving window 70 105 140 s r pgood power good pull- down on- resistance i = 10ma 8 12 30 v run enable pin input high input low l l 1 0.4 v v pull -down resistance 4 m e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3615/ltc3615-1 are tested under pulsed load conditions such that t j t a . the ltc3615e/ltc3615e-1 are guaranteed to meet performance specifications over the 0c to 85c operating junction temperature range. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3615i/ltc3615i-1 are guaranteed to meet specifications over the C40c to 125c operating junction temperature range. the ltc3615h/ltc3615h-1 are guaranteed to meet specifications over the C40c to 150c operating temperature range. the ltc3615mp/ltc3615mp-1 are tested and guaranteed to meet specifications over the full C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetime; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. note 3: this parameter is tested in a feedback loop which servos v fb1,2 to the midpoint for the error amplifier (v ith1,2 = 0.75v). note 4: external compensation on ith pin. note 5: tying the ith pin to sv in enables internal compensation and avp mode for the selected channel. note 6: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 7: see description of the track/ss pin in the pin functions section. note 8: when sourcing current, the average output current is defined as flowing out of the sw pin. when sinking current, the average output current is defined as flowing into the sw pin. sinking mode requires the use of forced continuous mode. note 9: see description of the mode pin in the pin functions section. note 10: guaranteed by design and correlation to wafer level measurements for qfn packages. note 11: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability or permanently damage the device. the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2), sv in = pv inx = 3.3v, r t = 178k, r srlim = 40.2k, unless otherwise specified. ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
5 typical p er f or m ance c harac t eris t ics load regulation line regulation efficiency vs load current (v mode = 0v) efficiency vs load current (v mode = 0v) efficiency vs load current (v mode = 0v) v in = 3.3v , r t / sync = sv in , unless otherwise noted. efficiency vs load current (v mode = 0.55 ? sv in ) efficiency vs load current (v mode = 0.55 ? sv in ) efficiency vs input voltage (v mode = 0v) output current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 10 3615 g01 0 v out = 1.8v v in = 2.5v v in = 3.3v v in = 5v 0.001 0.1 1 0.01 output current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 3615 g02 0 v out = 1.2v v in = 2.5v v in = 3.3v v in = 5v 10 0.001 0.1 1 0.01 output current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 3615 g03 0 v out = 2.5v v in = 3.3v v in = 4v v in = 5v 10 0.001 0.1 1 0.01 output current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 3615 g04 0 v out = 1.8v v in = 2.25v v in = 3.3v v in = 5v 10 0.001 0.1 1 0.01 output current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 3615 g05 0 v in = 2.25v v in = 3.3v v in = 5v v out = 1.2v 10 0.001 0.1 1 0.01 input voltage (v) 2.25 50 efficiency (%) 55 65 70 75 95 90 3615 g06 60 85 80 3.75 3.25 5.25 2.75 4.25 4.75 i out = 3a i out = 2a i out = 1a i out = 0.3a i out = 0.2a v out = 1.8v output current (a) 0 v out error (%) 0.2 0.3 0.4 0.1 0 0.5 1.51 2 2.5 3 ?0.3 ?0.4 ?0.1 0.5 ?0.2 3615 g07 internal compensation (i th = sv in ) v mode = 1.5v external compensation input voltage (v) 2.25 v out error (%) 0.05 0.10 0.15 0 2.75 3.753.25 4.25 4.75 5.25 ?0.15 ?0.20 ?0.05 0.20 ?0.10 3615 g08 ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
6 load step transient in fcm with avp mode load step transient in fcm external compensation load step transient in pulse-skipping mode load step transient in burst mode operation v out 200mv/div i l 1a/div 50s/div 3615 g12 v out = 1.8v i load = 100ma to 3a v mode = 1.5v compensation figure 1 v out 200mv/div i l 1a/div 50s/div 3615 g13 v out = 1.8v i load = 100ma to 3a v mode = 3.3v compensation figure 1 v out 200mv/div i l 1a/div 50s/div 3615 g14 v out = 1.8v i load = 100ma to 3a v mode = 0v compensation figure 1 v out 100mv/div i l 1a/div 50s/div 3615 g15 v out = 1.8v i load = 100ma to 3a v mode = 1.5v v ith = 3.3v output capacitor value figure 1 pulse-skipping mode operation forced continuous mode operation (fcm) burst mode operation v out 20mv/div i l 200ma/div 1s/div 3615 g09 v out = 1.8v i out = 100ma v mode = 1.5v v out 20mv/div i l 500ma/div 20s/div 3615 g10 v out = 1.8v i out = 75ma v mode = 3.3v v out 20mv/div i l 500ma/div 20s/div 3615 g11 v out = 1.8v i out = 75ma v mode = 0v load step transient in forced continuous mode sourcing and sinking current v out 200mv/div i l 2a/div 0a 50s/div 3615 g16 v out = 1.8v i load = ?1.5a to 3a v mode = 1.5v compensation figure 1 internal start-up in forced continuous mode v out 500mv/div run 1v/div i l 1a/div pgood 2v/div 500s/div 3615 g17 v out = 1.8v i out = 3a v mode = 1.5v typical p er f or m ance c harac t eris t ics v in = 3.3v , r t / sync = sv in , unless otherwise noted. ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
7 typical p er f or m ance c harac t eris t ics switch on-resistance vs input voltage reference voltage vs temperature frequency vs input voltage frequency vs r t /sync frequency vs temperature v in = 3.3v , r t / sync = sv in , unless otherwise noted. r t /sync (k) 100 0 f osc (mhz) 3.6 0.8 1.2 1.6 4.0 2.4 300 500 600 1000 3615 g22 0.4 2.8 3.2 2.0 200 400 700 800 900 v in (v) 2.25 1.60 f osc (mhz) 1.80 1.90 2.00 2.10 2.60 2.50 2.40 2.30 3615 g24 1.70 2.20 4.50 3.75 5.25 3.00 r t /sync = sv in r t /sync = 200k v in (v) 2.25 0 r ds(on) () 0.01 0.03 0.04 0.05 0.10 0.09 0.08 0.07 3615 g19 0.02 0.06 4.25 3.25 5.25 main switch synchronous switch switch on-resistance vs temperature temperature (c) ?60 0.594 reference voltage (v) 0.596 0.600 0.602 0.604 150 3615 g18 0.598 ?25 10 45 80 115 0.606 temperature (c) ?60 switch leakage (a) 40 90 100 10 20 70 30 80 10 0 60 50 ?25 80 45 150115 3615 g20 main switch synchronous switch temperature (c) 1.8 f osc (mhz) 1.9 2.1 2.2 2.3 2.7 2.6 2.5 3615 g23 2.0 2.4 ?60 10?25 8045 115 150 r t /sync = sv in r t = 178k ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
8 typical p er f or m ance c harac t eris t ics switch leakage vs temperature no load supply current vs input voltage no load supply current vs temperature slew rate of falling edge at sw1/2 vs srlim resistor slew rate of rising edge at sw1/2 vs srlim resistor sinking current v out 20mv/div sw 2v/div i l 500ma/div 1s/div 3615 g30 v out = 1.2v i out = ?1a v mode = 1.5v tracking up/down in forced continuous mode, srlim pin tied to 0v v out1 1v/div v track/ss 500mv/div pgood 2v/div 2ms/div 3615 g31 v out = 0v to 1.8v i out = 3a v track/ss = 0v to 0.7v v mode = 1.5v v srlim = 0v tracking up/down in forced continuous mode, srlim pin tied to sv in v track/ss 200mv/div v out1 500mv/div pgood 2v/div 2ms/div 3615 g32 v out = 0v to 1.2v i out = 3a v track/ss = 0v to 0.4v v mode = 1.5v v srlim = 3.3v v in = 3.3v , r t / sync = sv in , unless otherwise noted. 2ns/div 3615 g28 srlim = sgnd or sv in v in = 3.3v v out = 1.8v i out = 1a open 100k 1v/div 40.2k 1v/div 2ns/div 3615 g29 srlim = sgnd or sv in v in = 3.3v v out = 1.8v i out = 1a open 100k 40.2k v in (v) 2.25 supply current (a) 3615 g26 3.25 3.75 2.75 5.25 4.25 4.75 80 180 40 140 60 160 20 0 120 100 mode = 0v runx = ithx = sv in temperature (c) ?60 switch leakage (a) 2.0 4.0 10 1.0 3.5 1.5 0.5 0 3.0 2.5 ?25 8045 115 150 3615 g25 synchronous switch main switch ?60 10 ?25 8045 115 150 temperature (c) supply current (a) 3615 g27 80 180 40 140 60 160 20 0 120 100 mode = 0v runx = ithx = sv in ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
9 p in func t ions phase (pin 1/pin 4): phase shift selection. if pin is tied to sgnd, the phase between sw1 and sw2 will be 0 (ltc3615) or 140 ( ltc3615-1). with the phase pin tied to half of the sv in voltage , 90 ( ltc3615) or 140 (ltc3615-1) of phase shift will be selected. tying phase to sv in will select 180 (ltc3615 and ltc3615-1). v fb2 (pin 2/pin 5): voltage feedback input pin for chan - nel 2. see v fb1 . ith 2 (pin 3/pin 6): error amplifier compensation of channel 2. see ith1. track/ss2 (pin 4 /pin 7): internal, external soft- start, external reference input for channel 2. see track/ ss1. sgnd (pin 5/pin 8): signal ground. all small-signal and compensation components should connect to this ground pin which, in turn, should be connected to pgnd at one point. pv in2 (pins 6, 7/pins 9, 10) channel 2 power supply input. see pv in1 . sw 2 (pins 8, 9/pins 11, 12): channel 2 switching node. see sw1. run 2 ( pin 10/ pin 13): enable pin for channel 2. see run1. run1 (pin 11/pin 14): enable pin for channel 1. forcing run1 above the input threshold enables the output sw1 of channel 1. forcing both runx pins to ground shuts down the ltc3615. in shutdown, all functions are disabled and the ltc3615 draws <1a of supply current. r t /sync (pin 12/pin 15): oscillator frequency. this pin provides three modes of setting the switching frequency. 1. connecting a resistor from r t /sync to ground will set the switching frequency based on the resistor value. 2. driving r t /sync with an external clock signal will synchronize the switcher to the applied frequency. the slope compensation is automatically adapted to the external clock frequency. 3. tying this pin to sv in enables the internal 2.25mhz oscillator frequency. pgood2 (pin 13/pin 16): power good output for channel 2. see pgood1. srlim ( pin 14 /pin 17): slew rate limit. slew rate on the switch pins is programmed with the srlim pin: 1. tying this pin to sgnd selects maximum slew rate. 2. minimum slew rate is selected when the pin is open. 3. connecting a resistor from srlim to sgnd allows the slew rate to be continuously adjusted. 4. if srlim is tied to sv in the slew rate is set to maxi- mum and ddr mode is enabled ( see the applications information section). pgood 1 (pin 15/pin 18): power good output pin for channel 1. the open-drain output will be pulled down to ground when the fb1 voltage of the channel is not within the power good voltage window. the pgood1 will also be pulled down if the channel is not enabled with the run1 pin or an undervoltage at sv in is detected. in ddr mode (srlim = sv in ), the power good window moves in relation to the actual track/ss pin voltage. sw1 (pins 17, 16/pins 19, 20): channel 1 switching node. connection to the external inductor. this pin con - nects to the drains of the internal synchronous power mosfet switches. pv in1 (pins 18, 19/pins 21, 22): channel 1 power supply inputs. these pins connect to the source of the internal power p-channel mosfet of channel 1. p vin1 and p vin2 are independent of each other. they may connect to equal or lower supplies than s vin . sv in (pin 20/pin 23) signal input supply. this pin pow- ers the internal control circuitry and is monitored by the under voltage lockout comparator. track/ss1 (pin 21/pin 24): internal, external soft-start, external reference input for channel 1. the type of start - up (fe/uf) ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
10 behavior for channel 1 is programmable with the track/ ss1 pin: 1. internal soft - start with a fixed timing can be programmed by tying track/ss1 to sv in . 2. external soft-start can be programmed with the timing set by a capacitor to ground and a resistor to sv in . 3. tracking the start-up behavior of another supply is programmable ( see the applications information section). 4. the pin can be used as external reference input. ith 1 (pin 22/pin 1): error amplifier compensation. con - nection for external compensation from ith to sgnd. the current comparators threshold increases with this control voltage. tying this pin to sv in enables avp mode with internal compensation. v fb1 (pin 23/pin 2): voltage feedback input pin for channel 1. receives the feedback voltage for channel 1 from the external resistive divider across the output. mode (pin 24/pin 3): mode selection. p in func t ions (fe/uf) 1. tying the mode pin to sv in or sgnd enables pulse- skipping mode or burst mode operation ( with an internal burst mode clamp), respectively. 2. if this pin is held at slightly higher than half of sv in , forced continuous mode will be selected. 3. connecting this pin to an external voltage will select burst mode operation with the burst clamp set to the pin voltage. pgnd ( exposed pad pin 25/ exposed pad pin 25): power ground. the exposed pad connects to the sources of the power n-channel mosfets. the pgnd pin is common for both channels. the exposed pad must be soldered to the pcb. for electrical connection and rated thermal performance, refer to the operation and applications information sec - tions for more information. ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
11 func t ional b lock diagra m ideal diode track/ss1 soft-start or v ref internal/ external compensation ith-voltage limit mode fb1 pgood1 r t /sync run2 run1 phase fb2 pgood2 track/ss2 sw2 pv in2 pv in1 sw1 pgnd sv in sgnd undervoltage lockout slope compensation nmos current sense pmos current sense controller logic gate driver ? + ? + ? + shutdown clk2 clk1 mode ith1 0a srlim burst comparator pgood window- comparator channel 1 error amplifier duplicate for channel 2 reverse current comparator pmos current comparator delay pll oscillator and phase selector ith2 +? +? 3615 fd ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
12 figure 1. mode selection voltage o pera t ion main control loop the ltc3615 is a dual monolithic step-down dc/dc converter featuring current- mode, constant - frequency operation. both channels are identical and share common clock and reference circuits to improve channel- to- channel matching. during normal operation, the internal top power switch (p-channel mosfet) of each channel is turned on at the beginning of its clock cycle. current in the inductor increases until the current comparator trips and turns off the top power mosfet. the peak inductor current at which the current comparator shuts off is controlled by the voltage on the ith pin. the error amplifier adjusts the voltage on the ith pin by comparing the feedback signals derived from an external resistor divider on the v fbx pin with an internal 0.6 v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error amplifier raises the ith voltage until the average inductor current matches the new load current. typical voltage range for the ith pin is from 0.45v to 1.05 v with 0.45 v corresponding to zero current. when the top power mosfet shuts off, the synchronous power switch ( n-channel mosfet) turns on until either the current limit is reached or the next clock cycle begins. the bottom current limit is typically set at C4 a for forced continuous mode and 0 a for burst mode operation and pulse-skipping mode. the operating frequency defaults to 2.25mhz when r t /sync is connected to sv in , or can be set by an ex- ternal resistor connected between the r t /sync pin and ground, or by a clock signal applied to the r t /sync pin. the switching frequency can be set from 400 khz to 4mhz (see the applications information section). overvoltage and undervoltage comparators pull the pgood output low if the output voltage varies more than 7.5% from the set point. mode selection the mode pin is used to select one of four different operating modes for both channels together ( see figures 1 and 3): burst mode operationinternal clamp connecting the mode pin to the sgnd pin enables burst mode operation with its peak current set internally. in burst mode operation the internal power mosfets operate intermittently at light loads. this increases efficiency by minimizing switching losses. during the intervals when the mosfets are not switching, the ltc3615 enters a sleep state where many of the internal circuits are disabled to save power. during burst mode operation, the ith volt- age is monitored by the burst comparator to determine when the sleep state is entered or exited again. when the average inductor current is greater than the load current, the voltage on the ith pin drops. as the ith voltage falls below the internal threshold, the ltc3615 enters the sleep state. in the sleep state, the power mosfets are held off and the load current is solely supplied by the output capacitor. when the output voltage drops, the top power mosfet is switched back on and the internal circuits are reenabled. this process repeats at a rate that is dependent on the load current. ps pulse-skipping mode enable forced continuous mode enable burst mode enable?internal clamp 3615 f01 burst mode enable?external clamp, controlled by voltage applied at mode pin sv in sv in ? 0.3v sv in ? 0.58 1.1v 0.8v 0.5v 0.3v sgnd bm bm ext fc ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
13 burst mode operationexternal clamp connecting the mode pin to a voltage in the range of 0.5v to 0.8 v enables burst mode operation with external clamp. during this mode of operation, the minimum voltage on the ith pin is externally set by the voltage on the mode pin. it is recommended to use burst mode operation with the internal clamp for ambient temperatures above 85c. pulse-skipping mode operation pulse-skipping mode is similar to burst mode operation, but the ltc3615 does not disable power to the internal circuitry during sleep mode. this improves output voltage ripple but uses more quiescent current compromising light load efficiency. connecting the mode pin to sv in enables pulse-skipping mode. as the load current decreases, the peak inductor current will be determined by the voltage on the ith pin until the ith voltage drops below 450 mv, corresponding to 0 a. at this point switching cycles will be skipped to keep the output voltage in regulation. forced continuous mode operation in forced continuous mode the inductor current is con - stantly cycled which creates a minimum output voltage ripple at all output current levels. connecting the mode pin, to a voltage in the range of 1.1v to sv in ? 0.58 will select the forced continuous mode operation. the forced continuous mode must be used if the output is required to sink current. dropout operation as the input supply voltage approaches the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle, eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor. o pera t ion figure 2. modes of operation ltc3615 sv in v in mode sgnd 0v 2a. burst mode operation internally controlled ltc3615 sv in v in mode sgnd 0v 2c. pulse-skipping mode ltc3615 sv in v in mode sgnd 0v r m1 r m2 3615 f02 2d. forced continuous mode 2b. burst mode operation externally controlled ltc3615 sv in v in mode sw1 fb1 sgnd 0v v out1 r m1 r m2 ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
14 low supply operation the ltc3615 is designed to operate down to an input supply voltage of 2.25 v. an important consideration at low input supply voltages is that the r ds(on) of the p-channel and n-channel power switches increases by 50% compared to 5v. the user should calculate the power dissipation when the ltc3615 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. slope compensation and inductor peak current slope compensation provides stability in current mode constant-frequency architectures by preventing subhar - monic oscillations at duty cycles greater than 50%. the ltc3615 implements slope compensation by adding a compensation ramp to the inductor current signal. short-circuit protection the peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the ith pin. if the output current increases, the error amplifier raises the ith pin voltage until the average inductor current matches the new load current. in normal operation, the ltc3615 clamps the maximum ith pin voltage at ap - proximately 1.05 v which corresponds to about 5 a peak inductor current. when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. the ltc3615 uses two techniques to prevent current runaway from occurring: 1. if the output voltage drops below 50% of its nominal value, the clamp voltage at pin ith is lowered, causing the maximum peak inductor current to lower gradu - ally with the output voltage. when the output voltage reaches 0 v, the clamp voltage at the ith pin drops to 40% of the clamp voltage during normal operation. the short-circuit peak inductor current is determined by the minimum on-time of the ltc3615, the input voltage and the inductor value. this foldback behavior helps in limiting the peak inductor current when the output is shorted to ground. it is disabled during internal or external soft-start and tracking up/down operation (see the applications information section). 2. if the inductor current of the bottom mosfet increases beyond 6 a typical, the top power mosfet will be held off and switching cycles will be skipped until the induc - tor current reduces. o pera t ion ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
15 operating frequency selection of the operating frequency is a trade-off between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency of the ltc3615 is determined by an external resistor that is connected between pin r t / sync and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r t = 4 ? 10 11 hz f osc although frequencies as high as 4 mhz are possible, the minimum on-time of the ltc3615 imposes a minimum limit on the operating duty cycle. the minimum on-time a pplica t ions i n f or m a t ion is typically 60 ns, therefore, the minimum duty cycle is equal to 60ns ? 100% ? f osc (hz) tying the r t /sync pin to sv in sets the default internal operating frequency to 2.25mhz 20%. frequency synchronization the ltc3615s internal oscillator can be synchronized to an external frequency by applying a square wave clock signal to the r t /sync pin. during synchronization, the top mosfet turn-on of channel 1 is locked to the rising edge of the external frequency source. the synchronization frequency range is 400 khz to 4 mhz. the internal slope compensation is automatically adapted to the external clock frequency. in the signal path from the r t /sync clock input to the sw output, the ltc3615 is processing the external clock frequency through an internal pll. after detecting an external clock on the first rising edge of r t /sync the pll starts up with the internal default of 2.25mhz. the internal pll then requires a certain number figure 3. soft-start and compensation for channel 1 externally programmed, soft-start and compensation for channel 2 internally programmed (2) sw1 fb1 mode ltc3615 3615 f03 sgnd pgnd run1 track/ss1 r t , 200k ith1 phase run2 track/ss2 pgood2 ith2 pgood1 r t /sync srlim v in 3.3v sv in (2 ) pv in1 (2 ) pv in2 1f 47f 47f 0.47h 47f v out1 1.8v/3a r1 422k r2 29.4k r3 178k r ss 4.7m c ss 10nf r c 15k c c 1000pf (2) sw2 fb2 0.47h 47f v out2 2.5v/3a r5 665k r4 210k 10pf r srlim 40.2k ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
16 ltc3615 sv in v in r t /sync ltc3615 sv in v in 0.4v r t /sync r osc sgnd f sw 2.25mhz f sw 1/r osc 3615 f04 ltc3615 sv in f sw 1/t p v in r t /sync sgnd t p 1.2v 0.3v f sw 1/t p t p 1.2v 0.3v ltc3615 sv in v in r t /sync sgnd 15pf r t on the duty cycle of the two channels, choose the phase difference between the channels to keep edges as far away from each other as possible. for example, for duty cycles of less than 40% for one channel and more than 60% for the other channel, the sw node edges will not coincide for 0 or 180 phase shifts. if both channels have a duty cycle of around 50%, a 90 phase difference would be a better choice. in cases where the duty cycles are ~25% and ~50%, a 140 phase shift ( ltc3615-1 only) is preferable to the other phase selections. inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current ?i l increases with higher v in and decreases with higher inductance. i l = v out f sw ? l ? ? ? ? ? ? ? 1C v out v in(max) ? ? ? ? ? ? ? ? having a lower ripple current reduces the core losses in the inductor, the esr losses in the output capacitors and the output voltage ripple. a reasonable starting point for selecting the ripple current is ?i l = 0.3(i out(max) ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: l = v out f sw ? i l(max) ? ? ? ? ? ? ? ? ? 1C v out v in(max) ? ? ? ? ? ? ? ? the inductor value will also have an effect on burst mode operation. the transition to low current operation begins figure 4. setting the switching frequency a pplica t ions i n f or m a t ion of periods to settle until the frequency at sw matches the frequency and phase of r t /sync. when the external clock signal is removed, the ltc3615 needs approximately 5 s to detect the absence of the external clock. during this time, the pll will continue to provide clock cycles before it is switched back to the de - fault frequency or selected frequency ( set via the external r t resistor). a safe way of driving the r t /sync input is with an ac coupling to the clock generator via a 15pf capacitor. the ac coupling avoids complications if the external clock generator cannot provide a continuous clock signal at the time of start- up, operation and shut down of the ltc3615. in general, any abrupt clock frequency change of the regulator will have an effect on the sw pin timing and may cause equally sudden output voltage changes. this must be taken into account in particular if the external clock frequency is significantly different from the internal default of 2.25mhz. phase selection channel 2 of the ltc3615 will operate in-phase , 180 out-of-phase ( anti-phase) or shifted by 90 from chan - nel 1 depending on the state of the phase pinlow, midrail and high, respectively. channel 2 of ltc3615-1 will operate 180 out-of-phase ( anti-phase) with phase pin high or shifted by 140 with phase midrail or low. antiphase generally reduces input voltage and current ripple. crosstalk between switch nodes sw1, sw2 and components or sensitive lines connected to fbx, ithx, r t / sync or srlim can cause unstable switching waveforms and unexpectedly large input and output voltage ripple. the situation improves if rising and falling edges of the switch nodes are timed carefully not to coincide. depending ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
17 when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower dc load currents. this causes a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for fixed inductor value, but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire, and therefore, copper losses will increase. ferrite designs have very low core losses and are pre - ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing satura- tion. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow a ferrite core to saturate and select external inductors respecting the temperature range of the application! different core materials and shapes will change the size/ current and price/current relationship of an inductor. t oroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. table 1 shows some typical surface mount inductors that work well in ltc3615 applications. input capacitor c in selection in continuous mode, the source current of the top p- channel mosfet is a square wave of duty cycle v out / v in . to prevent large voltage transients, a low esr capacitor sized for the maximum rms current must be used for c in . the maximum rms capacitor current is given by: i rms = i out(max) ? v out v in ? v in v out C 1 ? ? ? ? ? ? this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst - case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. generally select the capacitors respecting the temperature range of the application! several capacitors may also be paralleled to meet size or height requirements in the design. a pplica t ions i n f or m a t ion table 1. representative surface mount inductors inductance (h) dcr (m) max current (a) dimensions (mm) height (mm) vishay ihlp-2020bz-01 0.33 7.6 25 5.18 5.49 2 0.47 8.9 21 5.18 5.49 2 0.68 11.2 15 5.18 5.49 2 1 18.9 16 5.18 5.49 2 toko de3518c series 0.22 8 24 4.3 4.7 2 sumida cdmc6d28 series 0.3 3.2 15.4 6.7 7.25 3 0.47 4.2 13.6 6.7 7.25 3 0.68 5.4 11.3 6.7 7.25 3 1 8.8 8.8 6.7 7.25 3 nec/tokin mplc0730l series 0.47 4.5 16.6 6.9 7.7 3.0 0.75 7.5 12.2 6.9 7.7 3.0 1.0 9.0 10.6 6.9 7.7 3.0 coilcraft do1813h series 0.33 4 10 8.9 6.1 5 0.56 10 7.7 8.9 6.1 5 coilcraft slc7530 series 0.27 0.1 14 7.5 6.7 3 0.35 0.1 11 7.5 6.7 3 0.4 0.1 8 7.5 6.7 3 ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
18 output capacitor c out selection the selection of c out is typically driven by the required esr to minimize voltage ripple and load step transients (low-esr ceramic capacitors are discussed in the next section). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ?v out is determined by: v out i l ? esr + 1 8 ? f sw ? c out ? ? ? ? ? ? where f sw = operating frequency, c out = output capacitance and ?i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since ? i l increases with input voltage. in surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, esr or rms current handling requirement of the application. aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. tantalum capacitors have the highest capacitance density, but can have higher esr and must be surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can often be used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic input and output capacitors ceramic capacitors have the lowest esr and can be cost effective, but also have the lowest capacitance density, high voltage and temperature coefficients, and exhibit audible piezoelectric effects. in addition, the high-q of ceramic capacitors along with trace inductance can lead to significant ringing. capacitors are tempting for switching regulator use because of their very low esr. great care must be taken when using only ceramic input and output capacitors. ceramic caps are prone to temperature effects which re- quire the designer to check loop stability over the operating temperature range. to minimize their large temperature and voltage coefficients, only x5r or x7r ceramic capaci - tors should be used. when a ceramic capacitor is used at the input, and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v in pin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, the ringing at the input can be large enough to damage the part. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation com - ponents and the output capacitor size. typically, three to four cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. the output droop, v droop , is usually about two to three times the linear drop of the first cycle. thus, a good place to start is with the output capacitor size of approximately: c out 2.5 ? i out f sw ? v droop more capacitance may be required depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. a pplica t ions i n f or m a t ion ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
19 output voltage programming the output voltages are set by external resistive dividers. for example, v out2 can be set according to the following equation: v out2 = 0.6v ? 1 + r5 r4 ? ? ? ? ? ? the resistive divider allows pin v fb to sense a fraction of the output voltage as shown in figure 3. burst clamp programming if the voltage on the mode pin is less than 0.8 v, burst mode operation is enabled. if the voltage on the mode pin is less than 0.3 v, the internal default burst clamp level is selected. the minimum voltage on the ith pin is typically 525mv (internal clamp). if the voltage is between 0.45 v and 0.8 v, the voltage on the mode pin (v burst ) is equal to the minimum voltage on the ith pin ( external clamp) and determines the burst clamp level i burst (typically from 1a to 3.5a). when the ith voltage falls below the internal ( or external) clamp voltage, the sleep state is entered. as the output load current drops, the peak inductor current decreases to keep the output voltage in regulation. when the output load current demands a peak inductor current that is less than i burst , the burst clamp will force the peak inductor current to remain equal to i burst regardless of further reductions in the load current. since the average inductor current is greater than the output load current, the voltage on the ith pin will decrease. when the ith voltage drops, sleep mode is enabled in which both power switches are shut off along with most of the circuitry to minimize power consumption . all circuitry is turned back on and the power switches resume operation when the output voltage drops out of regulation. the value for i burst is determined by the desired amount of output voltage ripple. as the value of i burst increases, the sleep period between pulses and the output voltage ripple increase. it is recommend to use burst mode operation with internal clamp for tem - peratures above 85 c ambient. pulse-skipping mode pulse- skipping mode, which is a compromise between low output voltage ripple and efficiency, can be implemented by connecting the mode pin to sv in . this sets i burst to 0a. in this condition, the peak inductor current is limited by the minimum on-time of the current comparator. the lowest output voltage ripple is achieved while still operating discontinuously. during very light output loads, pulse- skipping allows only a few switching cycles to skip while maintaining the output voltage in regulation. internal and external compensation the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc load current. when a load step occurs, like the one shown in figure 5, v out shifts by an amount equal to ?i load ? esr, where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out , generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time, v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the ith pin allows the transient response to be optimized over a wide range of output capacitance. the ith1 external components (15 k and 100pf) shown in figure 3 will provide an adequate compensation as well as a starting point for most applications. the values can be modified slightly to optimize transient response once the final pcb layout is complete and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. the gain of the loop will be increased by increas- ing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stabil - ity of the closed- loop system. the external compensa - tion, for ced continuous operation circuit in the typical a pplica t ions i n f or m a t ion ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
20 50s/div 3615 f05 v out 200mv/div i l 1a/div 100ma 3a v out = 1.8v i load = 100ma to 3a v mode = 1.5v compensation and output capacitor values of figure 3 v out 100mv/div i l 1a/div 50s/div 3615 f06 v out = 1.8v i load = 100ma to 3a v mode = 1.5v v in = v ith = 3.3v output capacitor value figure 3 figure 6. load step transient in fcm in avp mode figure 5. load step transient in fcm with external compensation applications section uses faster compensation to improve load step response. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. more output capacitance may be required depending on the duty cycle and load step requirements. if the ith pin is tied to sv in , the active voltage positioning ( avp ) mode and the internal compensation is selected. in avp mode, the load regulation performance is inten - tionally reduced, setting the output voltage at a point that is dependent on the load current. when the load current suddenly increases, the output voltage starts from a level slightly higher than nominal so the output voltage can droop more and stay within the specified voltage range. when the load current suddenly decreases, the output voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the specified voltage range. this behavior is demonstrated in figure 6. the benefit is a lower peak- to- peak output voltage deviation for a given load step without having to increase the output filter capacitance. alternatively, the output voltage filter capacitance can be reduced while maintaining the same peak-to-peak transient response. for this operation mode, the loop gain is reduced and no external compensation is required. programmable switch pin slew rate as switching frequencies rise, it is desirable to minimize the transition time required when switching to minimize power losses and blanking time for the switch to settle. however, fast slewing of the switch node results in relatively high external radiated emi and high on-chip supply transients, which can cause problems for some applications. a pplica t ions i n f or m a t ion ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
21 (7a) slew rate of rising edge at sw1/2 vs srlim resistor the ltc3615 allows the user to control the slew rate of the switching node sw by using the srlim pin. tying this pin to ground selects the fastest slew rate. the slowest slew rate is selected when the pin is open. connecting a resistor (between 10 k to 100 k) from srlim pin to ground adjusts the slew rate between the maximum and minimum values. the reduced dv/dt of the switch node results in a significant reduction of the supply and ground ringing, as well as lower radiated emi. see figure 7 a and the typical performance characteristics section for examples. reducing the slew rate causes a trade-off between ef - ficiency and low emi (see figure 7b). particular attention should be used with very high switching frequencies. using the slowest slew rate ( srlim open) can reduce the minimum duty cycle capability. soft-start the runx pins provide a means to shut down each chan - nel of the ltc3615. pulling both pins below 0.3 v places the ltc3615 in a low quiescent current shutdown state (i q < 1a). after enabling the ltc3615 by bringing either one or both runx pins above the threshold, the enabled channels enter a soft-start-up state. the type of soft-start behavior is set by the track/ssx pins. the soft-start cycle begins with an initial discharge pulse pulling down the track/ ssx pin to sgnd and discharging the external capacitor c ss (see figure 3). the initial discharge is adequate to discharge capacitors up to 33 nf. if a larger capacitor is required, connect the external soft-start resistor r ss to the run pin to fully discharge the capacitor. 1. tying this pin to sv in selects the internal soft-start circuit. this circuit ramps the output voltage to the final value within 1ms. 2. if a longer soft-start period is desired, it can be set externally with a resistor and capacitor on the track/ ssx pins as shown in figure 3. the voltage applied at the track/ssx pins sets the value of the internal refer - ence at v fb until track/ssx is pulled above 0.6 v. the external soft-start duration can be calculated by using the following equation: t ss = r ss ? c ss ? in sv in sv in C 0.6v ? ? ? ? ? ? 3. the track/ssx pin can be used to track the output voltage of another supply. regardless of either the internal or external soft-start state, the mode pin is ignored during start-up and the regulator defaults to pulse-skipping mode. in addition, the pgoodx pin is kept low, and the frequency foldback function is disabled. a pplica t ions i n f or m a t ion (7b) efficiency vs srlim resistor programming figure 7. slew rate and the srlim resistor 1v/div 2ns/div 3615 f07a srlim = sgnd or sv in v in = 3.3v v out = 1.8v i out = 1a open 40.2k 100k v in (v) 2.25 82 efficiency (%) 84 86 88 3.06 3.88 4.69 90 92 83 85 87 89 91 5.50 3615 07b v out = 1.8v i out = 1a fcm gnd or sv in open 40.2k 20k ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
22 output voltage tracking input if srlim is low, once v track/ss reaches or exceeds 0.6v the run state is entered, and the mode selection, power good and current foldback circuits are enabled. in the run state, the track/ss pin can be used to track down / up the output voltage of another supply. if the v track / ss again drops below 0.6 v, the ltc3615 enters the down- tracking state and the v out is referenced to the track/ ss voltage. if v track/ss reaches 0.1 v value the switching frequency is reduced by 4 x to ensure that the minimum duty cycle limit does not prevent the output from following the track/ss pin. the run state will resume if the v track/ ss again exceeds 0.6 v and the v out is referenced to the internal reference. through the track/ss pin, the output voltage can be set up to either coincidental or ratiometric tracking, as shown in figures 8 and 9. to implement the coincidental tracking waveform in figure 8, connect an extra resistive divider to the output of the master channel and connect its midpoint to the track/ss pin for the slave channel. the ratio of this divider should be selected the same as that of the slave channels feedback divider (figure 10). in this tracking mode, the master channels output must be set higher than slave channels output. to implement the ratiometric start-up in figure 9, no extra divider is needed; simply connect the track/ss pin to the other channels v fb pin (figure 12). a pplica t ions i n f or m a t ion figure 8. coincident start-up tracking figure 9. ratiometric start-up tracking figure 10. set for coincidentally tracking (r3 = r5, r4 = r6) figure 11. alternative set-up for coincident start-up tracking (r1 = r3, r2 = r3 = r5) figure 12. set-up for ratiometric tracking time v out1 v out2 output voltage 3615 f08 time 3615 f09 v out1 v out2 output voltage r3 r4 r1 r2 v out1 fb1 ltc3615 track/ss2 fb2 r5 r6 v out2 3615 f10 r2 r1 r3 v out1 fb1 ltc3615 track/ss2 fb2 r4 r5 v out2 3615 f11 r1 r2 v out1 fb1 ltc3615 track/ss2 fb2 r3 r4 v out2 3615 f12 ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
23 a pplica t ions i n f or m a t ion external reference input (ddr mode) if srlim is tied to sv in , the track/ss pin can be used as an external reference input between 0.3 v and 0.5 v, if desired (see figure 13). in ddr mode, the maximum slew rate is selected. if v track/ ss is within 0.3 v and 0.5v , the pgood function is enabled. if v track/ ss is less than 0.3v , the output current foldback is disabled and the pgood pin is always pulled down. figure 13. tracking if v srlim is low figure 14. tracking if v srlim is tied to sv in soft-start state t ss > 1ms shutdown state 0.6v 0.6v 0.1v 0v 0v 0v 0v v in v in v fb pin voltage track/ss pin voltage run pin voltage sv in pin voltage run state run state time 3615 f13 reduced switching frequency down- tracking state up- tracking state soft-start state t ss > 1ms shutdown state 0.3v 0.45v 0.45v 0.3v 0.1v 0v 0v 0v 0v v in v in v fb pin voltage external voltage reference 0.45v track/ss pin voltage run pin voltage sv in pin voltage run state run state time 3615 f14 reduced switching frequency down- tracking state up- tracking state ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
24 ddr application the ltc3615 can be used in ddr memory power supply applications by tying the srlim pin to sv in . in ddr mode, the maximum slew rate is selected. the output can both source and sink current. current sinking is typically limited to 1.5 a, for 1 mhz frequency and 1 h inductance, but can be lower at higher frequencies and low output voltages. if higher ripple current can be tolerated, smaller inductor values can increase the sink current limit. see the typical performance characteristics curves for more information. in addition, in ddr mode, lower external reference volt - ages and tracking output voltages between channels are possible. see the output v oltage tracking input section. single, low ripple 6a output application the lt3615 can generate a single, low ripple 6 a output if the outputs of the two switching regulators are tied together and share a single output capacitor ( see figure 15 on back of data sheet). in order to evenly share the current between the two regulators, it is needed to connect pins fb1 to fb2, ith1 to ith2 and to select forced continuous mode at the mode pin. to achieve lowest ripple , 90, or better, 180, antiphase is selected by connecting the phase pin to midrail or sv in . there are several advantages to this 2-phase buck regulator. ripple currents at the input and output are reduced, reducing voltage ripple and allowing the use of smaller, less expensive capacitors. although two inductors are required, each will be smaller than the inductor required for a single-phase regulator. this may be important when there are tight height restrictions on the circuit. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a per cent- age of input power. although all dissipative elements in the circuit produce a pplica t ions i n f or m a t ion losses, two main sources usually account for most of the losses: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of little consequence. 1. the v in quiescent current is due to two components: the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in due to gate charge, and it is typically larger than the dc bias current. both the dc bias and gate charge losses are proportional to v in , thus, their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw , and external inductor r l . in continuous mode the average output current flowing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc), as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses, including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% of the total loss. thermal considerations in most applications, the ltc3615 does not dissipate much heat due to its high efficiency. however, in ap - plications where the ltc3615 is running at high ambient ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
25 design example as a design example, consider using the ltc3615 in an application with the following specifications: v in = 3.3v to 5.5v v out1 = 2.5v v out2 = 1.2v i out1(max) = 1a i out2(max) = 3a i out(min) = 100ma f = 2.25mhz because efficiency is important at both high and low load current, burst mode operation will be selected by connect - ing the mode pin to sgnd. first, calculate the timing resistor: r rt /sync = 4e11 ? hz 2.25mhz = 178k next, calculate the inductor values for about 1 a ripple current at maximum v in : l1 = 2.5v 2.25mhz ? 1a ? ? ? ? ? ? ? 1C 2.5v 5.5v ? ? ? ? ? ? = 0.6h l2 = 1.2v 2.25mhz ? 1a ? ? ? ? ? ? ? 1C 1.2v 5.5v ? ? ? ? ? ? = 0.42h using a standard value of 0.56 h and 0.47 h inductors results in maximum ripple currents of: i l1 = 2.5v 2.25mhz ? 0.56h ? ? ? ? ? ? ? 1C 2.5v 5.5v ? ? ? ? ? ? = 1.08a i l2 = 1.2v 2.25mhz ? 0.47h ? ? ? ? ? ? ? 1C 1.2v 5.5v ? ? ? ? ? ? = 0.89a c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. for this design , 47 f ceramic capacitors will be used with x5r or x7r dielectric. c in should be sized for a maximum current rating of: i rms(max) = i out1 2 + i out2 2 = 2a rms a pplica t ions i n f or m a t ion temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 170 c, all four power switches will be turned off and the sw node will become high impedance. to prevent the ltc3615 from exceeding the maximum junction temperature, the user will need to do some ther - mal analysis . to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t rise = p d ? ja where p d is the power dissipated by the regulator, and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t a + t rise where t a is the ambient temperature. as an example, consider this case: the ltc3615 is in dropout at an input voltage of 3.3 v with a load current for each channel of 2 a at an ambient temperature of 70c. assuming a 20 c rise in junction temperature, to 90c, results in an r ds(on) of 0.086m ( see the graph in the typical performance characteristics section). therefore , the power dissipated by the part is: p d = (i 1 2 + i 2 2 ) ? r ds(on) = 0.69w for the qfn package, the ja is 37c/w. therefore, the junction temperature of the regulator op- erating at 70c ambient temperature is approximately: t j = 0.69w ? 37c/w + 70c = 95c note that for very low input voltage, the junction tem- perature will be higher due to increased switch resistance r ds(on) . it is not recommended to use full load current at high ambient temperature and low input voltage. to maximize the thermal performance of the ltc3615, the exposed pad should be soldered to a ground plane. see the pc board layout checklist. ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
26 decoupling the pv in with two 47 f capacitors is adequate for most applications. finally, it is possible to define the soft-start up time choos - ing the proper value for the capacitor and the resistor connected to track/ss pin. if one sets minimum t ss = 5ms and a resistor of 4.7 m, the following equation can be solved with the maximum sv in = 5.5v: c ss = 5ms 4.7m ? in 5.5v 5.5v C 0.6v ? ? ? ? ? ? = 9.2nf the standard value of 10 nf and 4.7 m guarantees the minimum soft-start time of 5 ms. in figure 3, channel 1 shows the schematic for this design example. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3615: 1. a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small signal components returning to the sgnd pin at one point which is then connected to the pgnd node at the exposed pad close to the ltc3615 2. connect the (+) terminal of the input capacitors, c in , as close as possible to the pv inx pins, and the (C) ter- minal as close as possible to the exposed pad pgnd. this capacitor provides the ac current into the internal power mosfets. 3. keep the switching nodes, swx, away from all sensitive small signal nodes fbx, ithx, rtsync, srlim. 4. flood all unused areas on all layers with copper. flood - ing with copper will reduce the temperature rise of power components. connect the copper areas to pgnd (exposed pad) for best performance. 5. connect the v fbx pins directly to the feedback resis- tors. the resistor divider must be connected between v outx and sgnd. a pplica t ions i n f or m a t ion ddr memory termination fb1 mode ltc3615 3615 ta03a sgnd pgnd run1 track/ss1 ith1 phase run2 track/ss2 pgood2 ith2 pgood1 r t /sync srlim v in 3.3v sv in c in1 47f c in2 47f c in3 1f l1 0.47h c out1 47f v ddq 1.8v/3a r1 121k r2 60.4k r7 15k c4 1000pf r10 15k c2 1000pf r3 150k r4 49.9k fb2 l2 0.47h c out2 47f r5 49.9k r6 49.9k c1 10pf c3 10pf r9 226k r8 174k v tt 0.9v 3a/?1.5a (2) sw1 (2 ) pv in1 (2 ) pv in2 (2) sw2 ratiometric start-up 3615 ta03b 500mv/ div 500s/div v dd v tt typical a pplica t ions ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
27 external compensation, forced continuous operation, in-phase switching, slew rate limit, common pgood output (2) sw1 fb1 mode ltc3615 3615 ta02 sgnd run1 track/ss1 r t 178k ith1 phase run2 track/ss2 pgood2 ith2 pgood1 r t /sync srlim mode v in 3.3v run pgood sv in (2 ) pv in1 (2 ) pv in2 0.47h 47f v out1 1.8v/3a r1 412k r2 205k r c2 43k c c2 220pf r c1 43k c c1 220pf (2) sw2 fb2 0.47h 47f v out2 2.5v/3a r3 665k r4 210k 10pf 10pf r5 40.2k 100k pgnd 1f 47f 47f r6 226k r7 174k typical a pplica t ions v out1 waveform v out2 waveform 3615 ta02b v out1 100mv/div i out1 1a/div 20s/div 3615 ta02c v out2 100mv/div i out2 1a/div 20s/div ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
28 typical a pplica t ions coincident start-up coincident tracking up/down 3615 ta04b 500mv/ div 2ms/div v out1 v out2 3615 ta04c 500mv/ div 200ms/div v out1 v out2 fb1 mode ltc3615-1 3615 ta04a sgnd pgnd run1 track/ss1 ith1 phase run2 track/ss2 pgood2 ith2 pgood1 r t /sync srlim v in 3.3v sv in c1 47f c2 47f l1 0.47h c o11 47f v out1 1.8v/3a c o12 22f r1 715k r2 357k r c2 15k c c3 470pf r c1 15k c c1 1000pf r3 453k r4 453k fb2 l2 0.47h c o21 47f r5 294k r6 294k c c2 10pf c c4 10pf c o22 22f v out2 1.2v/3a c f1 1f r f1 24 4.7m 10nf r7 100k r t 200k r5 100k c sync 15pf 2mhz clock pgood2 pgood1 c3 22pf c7 22pf (2) sw1 (2) sw2 (2 ) pv in1 (2 ) pv in2 r8 174k r9 226k master and slave for coincident tracking outputs using a 2mhz external clock ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
29 p ackage descrip t ion fe package 24-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1771 rev b) exposed pad variation aa fe24 (aa) tssop rev b 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 14 13 7.70 ? 7.90* (.303 ? .311) 3.25 (.128) 2.74 (.108) 2021222324 19 18 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.25 (.128) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 24-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1771 rev b) exposed pad variation aa ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
30 uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697 rev b) p ackage descrip t ion 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom view?exposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 rev b recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697 rev b) ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
31 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 7/10 ltc3615-1 added. reflected throughout the data sheet. 1 to 32 b 6/13 clarified temperature maximum ratings. clarified the ordering information section. clarified the feedback voltage specification in the electrical characteristics section. clarified the temperature specifications on notes 2 and 11. clarified typical performance characteristics graphs. clarified paragraphs in the inductor and input capacitor selection sections. clarified the maximum junction temperature in the thermal considerations section. 2 2 3 4 7, 8 17 25 ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615
32 ? linear technology corporation 2010 lt 0613 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3615 200ns/div 3615 f16 v sw1 2v/div, 1a/div v sw2 i l1 + i l2 i l2 i l1 mode = fcm r ela t e d p ar t s typical a pplica t ion part number description comments ltc3633 15v, dual 3a, 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 3.60v to 15v, v out(min) = 0.6v, i q = 500a, i sd < 13a, 4mm 5mm qfn-28 and tssop-28e packages ltc3546 5.5v, dual 3a/1a, 4mhz, synchronous step-down dc/ dc converter 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.6v, i q = 160a, i sd < 1a, 4mm 5mm qfn-28 package ltc3417a-2 5.5v, dual 1.5a/1a, 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 125a, i sd < 1a, tssop-16e and 3mm 5mm dfn-16 packages ltc3612 5.5v, 3a, 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 3mm 4mm qfn-20 and tssop-20e packages ltc 3614 5.5v, 4a, 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 3mm 4mm qfn-20 and tssop-20e packages ltc 3616 5.5v, 6a, 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 3mm 5mm qfn-24 package figure 15. single, low ripple 6a output (2) sw1 fb1 ltc3615 3615 f15 sgnd pgnd run1 track/ss1 ith1 phase run2 track/ss2 pgood2 ith2 pgood1 r t /sync mode srlim v in 3.3v sv in (2) pv in1 (2) pv in2 47f 1f l1 0.47h l2 0.47h v out 1.2v/6a 47f r1 102k r2 102k r c 7.5k c c 2000pf (2) sw2 fb2 20pf r8 226k r9 174k figure 16. reduced ripple current (waveform i l1 + i l2 ) and ripple voltage (not shown) through 180 phase shift between sw1 and sw2 figure 17. efficiency vs load current for v out = 1.2v and i out up to 6a output current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 30 20 10 0 90 100 3615 f17 v out = 1.2v mode = fcm v in = 2.5v v in = 3.3v v in = 5v ltc3615/ltc3615-1 3615fb for more information www.linear.com/ltc3615

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